Device scaling ensures that upcoming CMOS (Complementary metal-oxide semiconductor) technology nodes offer lower cost per function for a chip. However, dimensional scaling increases the importance of the local variation in charge at the semi-conductor-oxide interface. Statistical variation in charge is inversely proportional to the square root of the device gate area. Consequently, scaling results in device electrical performance (e.g., linear current, effective current, and threshold voltage) being more strongly affected by statistical fluctuations in the spatial variation of charge at the semi-conductor-oxide interface.
Conventionally identified and/or modeled sources of charge variation include: (i) random dopant fluctuation (RDF); (ii) dimensional variations (e.g., device length, device width, local channel length, fin width, fin height, and fin angle); (iii) work function variation (e.g. gate work function); (iv) granularity (e.g. metal grain granularity); and (v) oxygen vacancy concentration variation.